| OPBITS | pcen | ra2sel | werf | asel | bsel | aluop | memcmd | wdsel | pcsel |
| 0 HALT | |||||||||
| bad opcode (trapbit) | |||||||||
| 24 LD | |||||||||
| 25 ST | |||||||||
| 27 JMP | |||||||||
| 29 BRZ/zero | |||||||||
| 29 BRZ/not zero | |||||||||
| 30 BRNZ/zero | |||||||||
| 30 BRNZ/not zero | |||||||||
| 31 LDR | |||||||||
| 32..47 ADD, SUB... | |||||||||
| 48..63 ADDC... |
Use the table above to help you with Part 1 of Lab 2. Fill in the proper value for each of the switches. This table is probably arranged the way you'd normally think about the Beta switches: given a particular opcode, what value should each of the switches have? In other words, fill in each of the rows, one at a time.
The ROMs are programmed the other way around. For a particular switch, you need to figure out what value it should have for each opcode. In other words, look down each column to find patterns. Most of the switches are extremely simple, so it shouldn't be too hard to write. Don't panic, and you'll do fine.
| pcen = | _______________________________________________________ |
| ra2sel = | _______________________________________________________ |
| werf = | _______________________________________________________ |
| asel = | _______________________________________________________ |
| bsel = | _______________________________________________________ |
| aluop = | _______________________________________________________ |
| memcmd = | _______________________________________________________ |
| wdsel = | _______________________________________________________ |
| pcsel = | _______________________________________________________ |